1. Field of the Invention
This invention relates to an encoding and decoding apparatus for use with a magnetic recording channel, and in particular, to a run length limited (1,7) encoding and decoding apparatus that maps 2 unconstrained bits into 3 constrained bits.
2. Description Relative to the Prior Art
Run length limited codes, generically designated as (d,k) codes, have been widely and successfully applied in modern magnetic recording systems. They are extensions of earlier non return to zero recording codes, where binarily recorded "zeros" are represented by no flux change in the magnetic medium, while binary "ones" are represented by transitions from one direction of recorded flux to the opposite direction. In a (d,k) code, the above recording rules are maintained with the additional constraints that at least d "zeros" are recorded between successive data "ones", and no more than k "zeros" are recorded between successive data "ones". The first constraint arises to obviate intersymbol interference occurring due to pulse crowding of the reproduced transitions when a series of "ones" are contiguously recorded. The second constraint arises in recovering a clock from the reproduced data by "locking" a phase locked loop to the reproduced transitions. If there is too long an unbroken string of contiguous "zeros" with no interspersed "one" transitions, the clock generating Phase locked loop will fall out of synchronism. In a (1,7) code there is at least one "zero" inserted between the recorded "ones", and there are no more than seven recorded contiguous "zeros" between recorded "ones".
The "rate" of the code is a parameter which is a measure of its efficiency. The theoretical maximum rate of a code is called the Shannon capacity, and for a (1,7) code it has a value of 0.679. The implementation of practical codes requires that the rate be a rational fraction, and the code of the present invention is a rate 2/3 (1,7) code. This 2/3 rate, i.e. 0.667, is slightly less than the Shannon capacity, and the code is a therefore a highly efficient one. To achieve the 2/3 rate, 2 unconstrained data bits are mapped into 3 constrained encoded bits.
Rate 2/3 sliding block (1,7) codes and means for implementing associated encoders and decoders are known in the art. U.S. Pat. No. 4,413,251 entitled "Method and Apparatus for Generating A Noiseless Sliding Block Code for a (1,7) Channel with Rate 2/3", issued in the names of Adler et al, discloses an encoder which is a finite state machine having 5 internal states whose description requires 3 bits. Error propagation of Adler et al's (1,7) code does not exceed 5 data bits. U.S. Pat. No. 4,488,142 entitled "Apparatus for Encoding Unconstrained Data onto a (1,7) Format with Rate 2/3", issued in the name of Franaszek discloses an encoder having 8 internal states whose description also requires 3 bits. Franaszek's encoding technique utilizes "look ahead" at the upcoming data bits in the encoding of the current data bits, and error Propagation is 4 bits in bursts of 5.
The (1,7) codes of the above prior art are block codes, that is, the output codes are all of fixed length equal to 3 constrained bits. While the explicit mapping rules differ, and hardware implementation of the codes by means of encoders and decoders differ, each of the above block codes meets the conditions required of (1,7) codes with rate 2/3.